This invention relates to the buffer interface circuits on an integrated circuit (IC) which, at the inputs of the IC, translate the voltage levels of the input logic signals to the IC operating voltage levels; and, at the outputs of the IC, translate the voltage levels of the IC output logic signals back to the voltage levels with which the components off the IC operate.
In order to translate the generally higher voltage level logic signals employed by the circuitry off the IC to the generally lower voltage level IC logic signals, integrated circuits include a plurality of input buffers for converting each input signal applied to the IC. Similarly, a plurality of output buffers translates the plural lower voltage level logic IC signals back to the higher voltage level logic IC output signals. In translating these signals, each occurrence of a logical "0" and logical "1" voltage level in a higher level IC input signal is converted by an input buffer to a logical "0" and logical "1" voltage level, respectively, in a lower level signal. Similarly, an output buffer converts each occurrence of a logical "0" and logical "1" voltage level in the lower level IC signal to a logical "0" and logical "1" voltage level, respectively, in a higher level IC output signal. A buffer may not, however, instantaneously translate the transitions between logical "0" and logical "1" voltage levels at its input into corresponding transitions at its output. Furthermore, the propagation delay through a buffer of a transition from a low logical "0" voltage level to a high logical "1" voltage level is not likely to equal the propagation delay through that same buffer of a transition from a high logical "1" voltage level to a low logical "0" voltage level. As a result of this skew between the high-to-low and low-to-high propagation delays, the translated signal at the output of the buffer will be distorted in such a manner that the duration of a logical "0" or logical "1" pulse at the buffer output will be less than or greater than the corresponding pulses at the buffer input. For high-speed operations, such signal distortion can affect the ability of the circuitry on the IC and/or off the IC, to recognize the data bits. Buffer distortion can therefore limit the operating speed of the IC. Furthermore, such distortion is not readily eliminated a priori of manufacture since the magnitude of the distortion is not uniform from chip to chip, but is rather a variable, dependent upon processing, material, and enviromental conditions. As a result, a percentage of chips manufactured will have unacceptable performance characteristics at the desired operating speed, thereby reducing the usable yield of fabricated chips.
A high-speed logic level translator, disclosed in U.S. Pat. No. 4,305,009 to Y. Miyagawa et al., issued Dec. 8, 1981, speeds up the appearance of the level transition which is known a priori to be the slower of the two, using capacitive feed-forward techniques. Such a circuit will not eliminate the skew problem of an IC buffer where the low-to-high and high-to-low propagation delays are both variables, and there is no a priori knowledge of which transition is slower. In U.S. Pat. No. 4,314,166 to O. Bismarck, issued Feb. 2, 1982, a fast level shift circuit is disclosed which works as a translator to provide equal rise and fall times using a flip-flop memory element. The circuitry disclosed is moderately complex and may not perform satisfactorily at the high speeds where the asymmetry problems in buffers are the most severe.
The problem, then, is to devise a buffer arrangement for high-speed IC circuits that substantially reduces buffer distortion resulting from the difference in the low-to-high propagation delay with respect to the high-to-low propagation delay without any a priori knowledge of the sense or magnitude of that difference.